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 74LVT16373 * 74LVTH16373 Low Voltage 16-Bit Transparent Latch with 3-STATE Outputs
January 1999 Revised April 1999
74LVT16373 * 74LVTH16373 Low Voltage 16-Bit Transparent Latch with 3-STATE Outputs
General Description
The LVT16373 and LVTH16373 contain sixteen non-inverting latches with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear transparent to the data when the Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the outputs are in a high impedance state. The LVTH16373 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These latches are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT16373 and LVTH16373 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation.
Features
s Input and output interface capability to systems at 5V VCC s Bushold data inputs eliminate the need for external pullup resistors to hold unused inputs (74LVTH16373), also available without bushold feature (74LVT16373). s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free bus loading s Outputs source/sink -32 mA/+64 mA s Functionally compatible with the 74 series 16373 s Latch-up performance exceeds 500 mA
Ordering Code:
Order Number 74LVT16373MEA 74LVT16373MTD 74LVTH16373MEA 74LVTH16373MTD Package Number MS48A MTD48 MS48A MTD48 Package Descripion 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbol
(c) 1999 Fairchild Semiconductor Corporation
DS012021.prf
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74LVT16373 * 74LVTH16373
Connection Diagram
Pin Descriptions
Pin Names OEn LEn I0-I15 O0-O15 Description Output Enable Input (Active LOW) Latch Enable Input Inputs 3-STATE Outputs
Truth Tables
Inputs LE1 X H H L OE1 H L L L Inputs LE2 X H H L OE2 H L L L I8-I15 X L H X I0-I7 X L H X Outputs O0-O7 Z L H Oo Outputs O8-O15 Z L H Oo
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = HIGH Impedance Oo = Previous output prior to HIGH to LOW transition of LE
Functional Description
The LVT16373 and LVTH16373 contain sixteen D-type latches with 3-STATE standard outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. When the Latch Enable (LEn) input is HIGH, data on the Dn enters the latches. In this condition the latches are transparent, i.e, a latch output will change states each time its D input changes. When LEn is LOW, the latches store information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LEn. The 3-STATE standard outputs are controlled by the Output Enable (OEn) input. When OEn is LOW, the standard outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches.
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74LVT16373 * 74LVTH16373
Logic Diagrams
Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74LVT16373 * 74LVTH16373
Absolute Maximum Ratings(Note 1)
Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value -0.5 to +4.6 -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -50 -50 64 128 64 128 -65 to +150 Output in 3-STATE Output in HIGH or LOW State (Note 2) VI < GND VO < GND VO > VCC VO > VCC Output at HIGH State Output at LOW State mA mA mA mA mA C Conditions Units V V V
Recommended Operating Conditions
Symbol VCC VI IOH IOL TA t/V Supply Voltage Input Voltage HIGH Level Output Current LOW Level Output Current Free-Air Operating Temperature Input Edge Rate, VIN = 0.8V-2.0V, VCC = 3.0V -40 0 Parameter Min 2.7 0 Max 3.6 5.5 -32 64 85 10 mA C ns/V Units V V mA
Note 1: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 2: IO Absolute Maximum Rating must be observed.
DC Electrical Characteristics
Symbol Parameter VCC (V) 2.7 2.7-3.6 2.7-3.6 2.7-3.6 2.7 3.0 VOL Output LOW Voltage 2.7 2.7 3.0 3.0 3.0 II(HOLD) (Note 4) II(OD) (Note 4) II Bushold Input Over-Drive Current to Change State Input Current Control Pins Data Pins IOFF IPU/PD IOZL IOZH Power Off Leakage Current Power up/down 3-STATE Output Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current 3.6 3.6 -5 5 A A 3.0 3.6 3.6 3.6 0 0-1.5V Bushold Input Minimum Drive 3.0 75 -75 500 -500 10 1 -5 1 100 100 A A A A VCC - 0.2 2.4 2.0 0.2 0.5 0.4 0.5 0.55 A V 2.0 0.8 V V T A = -40C to +85C Min Typ (Note 3) VIK VIH VIL VOH Input Clamp Diode Voltage Input HIGH Voltage Input LOW Voltage Output HIGH Voltage -1.2 V V II = -18 mA VO 0.1V or VO VCC - 0.1V IOH = -100 A IOH = -8 mA IOH = -32 mA IOL = 100 A IOL = 24 mA IOL = 16 mA IOL = 32 mA IOL = 64 mA VI = 0.8V VI = 2.0V (Note 5) (Note 6) VI = 5.5V VI = 0V or VCC VI = 0V VI = VCC 0V VI or VO 5.5V VO = 0.5V to 3.0V VI = GND or VCC VO = 0.5V VO = 3.0V Max Units Conditions
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74LVT16373 * 74LVTH16373
DC Electrical Characteristics
Symbol IOZH+ ICCH ICCL ICCZ ICCZ+ ICC Parameter 3-STATE Output Leakage Current Power Supply Current Power Supply Current Power Supply Current Power Supply Current Increase in Power Supply Current (Note 7)
Note 3: All typical values are at VCC = 3.3V, TA = 25C. Note 4: Applies to bushold versions only (74LVTH16373).
(Continued)
T A = -40C to +85C Min Typ (Note 3) 3.6 3.6 3.6 3.6 3.6 3.6 10 0.19 5 0.19 0.19 0.2 A mA mA mA mA mA VCC < VO 5.5V Outputs HIGH Outputs LOW Outputs Disabled VCC VO 5.5V, Outputs Disabled One Input at VCC - 0.6V Other Inputs at VCC or GND Max Units Conditions
VCC (V)
Note 5: An external driver must source at least the specified current to switch from LOW to HIGH. Note 6: An external driver must sink at least the specified current to switch from HIGH to LOW. Note 7: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
Dynamic Switching Characteristics
Symbol VOLP VOLV Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL VCC (V) 3.3 3.3
(Note 8)
TA = 25C Min Typ 0.8 -0.8 Max Units V V Conditions CL = 50 pF, RL = 500 (Note 9) (Note 9)
Note 8: Characterized in SSOP package. Guaranteed parameter, but not tested. Note 9: Max number of outputs defined as (n). n-1 data inputs are driven 0V to 3V. Output under test held LOW.
AC Electrical Characteristics
TA = -40C to +85C, CL=50pF, RL=500 Symbol Parameter Min tPHL tPLH tPHL tPLH tPZL tPZH tPLZ tPHZ tS tH tW tOSHL tOSLH
Note 10: All typical values are at VCC = 3.3V, TA = 25C. Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH).
VCC = 3.3V 0.3V Typ (Note 10) Max 3.9 3.8 4.2 4.3 4.3 4.3 4.7 5.0
VCC = 2.7V Min 1.5 1.5 1.9 1.6 1.3 1.0 1.5 2.0 0.8 1.1 3.0 1.0 1.0 1.0 1.0 Max 4.3 4.2 4.4 4.8 4.9 5.1 4.8 5.4
Units
Propagation Delay Dn to On Propagation Delay LE to On Output Enable Time Output Disable Time Setup Time, Dn to LE Hold Time, Dn to LE LE Pulse Width Output to Output Skew (Note 11)
1.5 1.5 1.9 1.6 1.3 1.0 1.5 2.0 1.0 1.0 3.0
ns ns ns ns ns ns ns ns
Capacitance (Note 12)
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VCC = Open, VI = 0V or VCC VCC = 3.0V, VO = 0V or VCC Typical 4 8 Units pF pF
Note 12: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
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74LVT16373 * 74LVTH16373
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48
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74LVT16373 * 74LVTH16373 Low Voltage 16-Bit Transparent Latch with 3-STATE Outputs
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.


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